cva6
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
This PR adds basic support for Digilent Nexys Video Artix-7 FPGA. The FPGA device is XC7A200T and is supported by Vivado WebPACK version. Notable performance and functionality issues comparing with...
Hello 👋🏽 Dromajo co-simulation pass was broken due to the directory restructuring that happened after transferring Ariane to openhwgroup. This pull request includes: - fixes the Dromajo and should address...
Our co-simulation framework found that the mstatus.sd field does not update immediately after mstatus.fs field is dirty. In the following test case, we set mstatus.fs field to initial(0b01), and then...
This bug was initially reported in #708. > Consider the following scenario while executing from nonidempotent memory: > > 1. A branch instruction is fetched => `speculative_d = 1'b1` >...
Prevent deadlock when replaying speculative instruction from nonidempotent memory region. Consider the following scenario while executing from nonidempotent memory: 1. A branch instruction is fetched => `speculative_d = 1'b1` 2....
@JeanRochCoulon Add new fields to rvfi_instr_t in rvfi_pkg to handle exception cause and user fields. Guillaume
### Is there an existing CVA6-SDK task for this? - [X] I have searched the existing task issues ### Task Description Integrate Linux Boot on Genesys2 FPGA to Thales-CI Verification....
Hello all, I am trying to develop an Ethernet driver for u-Boot on a Genesys2 using as a starting point the lowRISC Ethernet driver for Linux, but I have encountered...
### Is there an existing CVA6-SDK task for this? - [X] I have searched the existing task issues ### Task Description Core-v-FreeRTOS Project Launch is done. Once the project is...
### Is there an existing CVA6-SDK task for this? - [X] I have searched the existing task issues ### Task Description Demonstration of mechanism to transform cache ways into a...