asic topic

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

secworks

An Implementation of CAdES, XAdES, PAdES and ASiC for Windows in C++

WindowsNT

Cryptocurrency ASIC mining hardware monitor using a simple web interface

anselal

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

pulp-platform

VUnit is a unit testing framework for VHDL/SystemVerilog

VUnit

Various HDL (Verilog) IP Cores

ultraembedded

Haskell to VHDL/Verilog/SystemVerilog compiler

clash-lang

SERV - The SErial RISC-V CPU

olofk

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

The-OpenROAD-Project

RISC-V CPU Core (RV32IM)

ultraembedded