systemverilog-hdl topic
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systemverilog-hdl repositories
vunit
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VUnit is a unit testing framework for VHDL/SystemVerilog
cva6
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
ISP_UVM
83
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36
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A Framework for Design and Verification of Image Processing Applications using UVM
easyUVM
33
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15
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A simple UVM example with DPI
axi_mem_if
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24
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Simple single-port AXI memory interface
PeakRDL-regblock
47
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Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
100DaysofRTL
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100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge d...
uvm-components
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Contains commonly used UVM components (agents, environments and tests).
morty
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A SystemVerilog source file pickler.