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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
CVA6 do not support dualread and dualwrite from a Coprocessor. Also, related to dualwrite: It is mentioned in the cvxif spec, that **we** is 2 bits wide when XLEN =...
If commit_valid is 1 and commit_kill is 0, then the core guarantees that the offloaded instruction (id) is no longer speculative, will not get killed (e.g. due to misspeculation or...
Hi, Our test case shows that Spike and cva6 throw different exceptions when executing the ``sret`` instruction with a specific ``sip`` value. The Spike throws ``instruction_access_fault`` at line 87, as...
CVXIF feature missing: wait for the result of the instruction that raise the issue resp.exc signal
CPU shall wait for the result of an instruction that raises the issue_resp.exc=1 signal (by the coprocessor), because it can then no longer retire (or commit via the commit interface)...
I try to run CI test of travis-ci-emul.sh in my local environment. When i run torture-rtest-verilator, there are two problem: 1. make torture-gen touture version in get-torture.sh is 59b0f0 which...
Hi, The RISC-V ISA Volume I, 20190608, page 43 mentions: "MULH[[S]U] rdh, rs1, rs2; MUL rdl, rs1, rs2 (source register specifiers must be in same order and rdh cannot be...
Hi, CVA6 RTL is returning unknown value ("xxxxxxxx") when reading the value of MHPMCOUNTER30. This is happening because the csr reg data (```csr_rdata```) is being read from ``perf_counter_d`` array in...
Hi, Our test cases show that when cva6 jumps to an invalid address (e.g., 0x7ff84538), it throws an Instruction Page Fault exception (at 22990ns). However, we believe it should throw...
Hi! I'm trying to simulate the hello.elf on questasim with the command: make sim elf-bin=$RISCV/riscv64-unknown-elf/bin/pk target-options=hello.elf batch-mode=1 My Questasim version 2019.2 Linux_x86_64 It seems to run and start loading all...
In the cvxif Spec, we have the following: - The transaction signaled via issue_req and issue_resp is accepted when issue_valid and issue_ready are both 1. - A CPU is allowed...
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux