cva6

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../configure: No such file or directory

1

error while running following code from [README.md](https://github.com/openhwgroup/cva6#running-user-space-applications): mkdir build cd build ../configure --prefix=$RISCV --host=riscv64-unknown-elf ERROR: ../configure: No such file or directory the configure file seems to be missing from root...

Rayz-b

Cannot view memory address contents through OpenOCD GDB debugging (FPGA emulation)

1

Hi, I am new to OpenOCD and debugging through FPGA emulation. So, pardon if any of the following seem trivial. I am using the Digilent 2 board for emulation purposes....

hasanalshaikh

common_cells folder location in cva6 repo

2

In current folder structure of cva6 repo "common_cells" folder has been placed in "cva6\core\fpu\src\" . Will it be a good idea to place "common_cells" inside "cva6\core".

nathpranay

Multi-issue support

2

Hi. Apparently there was a branch implementing multi-issue, but it doesn't exist anymore. What happened to that? Does ariane not support multi issue?

faridsamandi

Hi, I am trying to simulate Ariane using VCS and it could be appreciated if anyone share the verilog tetsbench of Ariane. Thanks in advance.

SreeRanjaniRajendran

Questasim + bare-metal program + physical memory access

3

I am in currently in the process of integrating a DMA engine into the CVA6 SoC. I would like to write a simple driver i.e. for the start, just read...

andreaskuster

Hello, As part of a personal project, I am working on adding a prefetcher for CVA6. To test its performance, I would like to run some benchmarks like SPEC or...

imadassir

make verilate failed.

3

I was trying to use RISCV toolchain with the Ariane core from https://github.com/openhwgroup/cva6 in macbook pro, I used homebrew to build riscv-toolchain and trying to build it, but while running...

SreeRanjaniRajendran

Cache Subsystem Doc

3

Hello, Is there any documentation on the OpenPiton compatible 'wt_cache_subsystem' that describes the structure and functioning of the subsystem? I am trying to understand the D$ which has 2-way SRAM...

kirateys

Documentation of "make fpga" for 32 bit

3

@zarubaf Current documentation says " Generating a Bitstream To generate the FPGA bitstream (and memory configuration) yourself for the Genesys II board run: make fpga " With reorg and changes...

nathpranay