cva6
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openhwgroup
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
### Is there an existing CVA6-SDK task for this? - [X] I have searched the existing task issues ### Task Description There is separate RISCV Portable area which has architectural...
Our co-simulation framework found that the exception type of address translation PMA violation is incorrect. In the following test case, we modify a non-leaf (level 2) PTE to zero, which...
Our co-simulation framework found that the exception type when access/load/store an illegal virtual address is incorrect. In the following test case, we flipped the MSB of a legal virtual address...
Hello ! I am intrigued by the behavior of an atomic instruction: **amoswap**. I observe the following behavior for amoswap rd, rs2, (rs1): ``` rd = M[rs1]; M[rs1]' = rs2;...
Our co-simulation framework found that the `*tval` of `ecall/ebreak` is incorrect. In cva6, after `ecall/ebreak`, *tval will set to the machine code of the `ecall/ebreak` instruction. In the following test...
Our co-simulation framework found that cva6 will truncate the address to use, specifically ignoring the highest 8 bits for pc and the highest 32 bits for load/store. Let's take the...
Hi there, I'm trying to dump vcd file using below command, but the 'rv64ui-p-add.vcd' file's size is 0 when the test finished. Can anyone help on this? work-ver/Variane_testharness -v rv64ui-p-add.vcd...
I have already make the command: make verilate DEBUG=1 succesfully to support vcd files. But when I try to make any test from Variane_testharness as : run a bare metal...
CVA6 always send the issue transaction and the commit transaction at the same clk cycle. It's allowed by the cvxif Spec, but if it is hard coded it may cause...
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux