cva6

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problem on work-ver/Variane_testharness rv64um-v-divuw

2

After the step make verilate DEBUG=1 on step work-ver/Variane_testharness rv64um-v-divuw i get the following error This emulator compiled with JTAG Remote Bitbang client. To enable, use +jtag_rbb_enable=1. Listening on port...

vulkomilev

I'm interested in bypassing the cache subsystem ([the data cache](https://github.com/openhwgroup/cva6/blob/master/core/cache_subsystem/wt_dcache.sv)) in an effort to communicate between the CPU and the main memory directly. However, I'm running into issues regarding the...

j-silv

Segmentation fault using QuestaSim

3

Hello, The latest version of the repo (8d893fb647d758bed5876307c64caa6adbc89f97) triggers a segmentation fault when trying to simulate using QuestaSim. This does not happen with commit 00236be3d8552f93a0bebda8f9820ec54b64a000 . The steps I have...

davidmallasen

I was playing with a `cv32a6` variant. In `riscv-tests`, while ISA tests are compiled for both 32-bit and 64-bit, benchmarks will only be compiled for 64-bits when running [ci/build-riscv-tests.sh](https://github.com/openhwgroup/cva6/blob/master/ci/build-riscv-tests.sh) I'm...

pcotret

How to read/access the address of specific CSR register listed in https://github.com/openhwgroup/cva6/blob/master/docs/user_guide/cva6_ug_csr.adoc In other words how to visualize these CSR registers Please help me in this regard

SreeRanjaniRajendran

Hello, I was reading the source code of cva6 recently, but I was a little confused about the implementation of interrupt nesting. I didn't understand how was it implement interrupt...

LangQingjie

Hi, I try to implement the [meltdown attack](https://meltdownattack.com) on CVA6 but I have some problems. The purpose of the [meltdown attack](https://meltdownattack.com) is to try to use the load instruction to...

Hsiang0816

Support for MCYCLEH, MINSTRETH, CYCLEH, TIMEH and INSTRETH in 32-bit mode

1

Hi, In 32-bit mode it would be nice to get access to the full 64-bit wide cycle and instruction counters for precision timing. Currently there's an exception of code references...

spersvold

Questions regarding simulation with Questa

5

I am working to get the simulations described in the README running under Questa and I am running into issues. Before digging deeper, I'd like to know the following: 1)...

KeithoHimself

Inline Assembly code in cva6 -reg

2

Hi, anyone can suggest me how to run/compile a Inline Assembly code in cva6 core. Thanks in advance.

SreeRanjaniRajendran