OpenHW Group

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

openhwgroup

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

openhwgroup

Functional verification project for the CORE-V family of RISC-V cores.

openhwgroup

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

openhwgroup

4 stage, in-order, compute RISC-V core based on the CV32E40P

openhwgroup

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

openhwgroup

This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.

openhwgroup

CORE-V Family of RISC-V Cores

openhwgroup

RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

openhwgroup

4 stage, in-order, secure RISC-V core based on the CV32E40P

openhwgroup