[possible bug] Ariane-Ethernet: Failing to receive frames

[MazzellaL]

Hello all, I am trying to develop an Ethernet driver for u-Boot on a Genesys2 using as a starting point the lowRISC Ethernet driver for Linux, but I have encountered an odd behavior with the controller where most of the times the received frames contains only garbage. Whilst this might seem like a cache problem, disabling it is of no avail; furthermore, the frame content is not just "random" data, but it is instead an 8-byte pattern repeated for the size of the received frame.

Currently the driver is set to use 8 buffers. By looking at the RSR register each time I get a frame, I have observed an interesting behavior: assuming a value of 18XY, for y=0 or y=1 the frame is correct; else the frame contains garbage. X is indifferent.

As an example, this is what I observe: good example:

SRS value is 1821 (or 1810)
[lowrisc eth: recv] 
0018 3e02 e37f [...] (frame is valid)

bad example:

SRS value is 18fe
[lowrisc eth: recv]
0000 0000 2867 5464 0000 0000 2867 2664 
0000 0604 2867 2664 0000 0000 2867 [...] (frame is invalid)

If I change the number of buffers to 2 (changing address offset calculation accordingly) I can see that frames at first aren't correct, then it mostly receives correct data:

SRS value is 12[10, 0f, fe, ed, dc, cb, ba, 98] (frame is invalid)
SRS value is 12[87, 76, 65, 54, 43, 32, 31, (10?)] (frame is valid)

By dumping the memory that the Ethernet controller uses from u-Boot I can confirm this too is not a copying issue from the driver side, as the data shown matches the data I retreive. Addresses are always 64-bit aligned too. Network is point to point and therefore there is no external traffic.

In the defconfig for u-Boot I have added the following configurations:

CONFIG_DEFAULT_DEVICE_TREE="cv64a6_genesysII"
CONFIG_LOWRISC_ETH=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_64BIT=y			#unaffecting
CONFIG_DMA_ADDR_T_64BIT=y	#default for the previous, but better be safe than sorry...
CONFIG_PHY_REALTEK=y		#the Genesys2 is using a Realtek 8211E PHY

At boot time, this is what u-Boot tells regarding the Ethernet Controller:

clk_set_defaults(lowrisc-eth@30000000)
clk_set_default_parents: could not read assigned-clock-parents for 00000000bf761800
ofnode_read_prop: assigned-clock-rates: <not found>
ofnode_read_prop: tick-timer: <not found>
Lowrisc PHY read: addr = 1, reg = 2, out = 0x1c
Lowrisc PHY read: addr = 1, reg = 3, out = 0xc915
Lowrisc PHY write: addr = 1, reg = 0, val = 0x8000
Lowrisc PHY read: addr = 1, reg = 0, out = 0x1140
lowrisc-eth@30000000 connected to RealTek RTL8211E
Lowrisc PHY write: addr = 1, reg = 0, val = 0x8000
Lowrisc PHY write: addr = 1, reg = 18, val = 0x0
Lowrisc PHY read: addr = 1, reg = 18, out = 0x0
Lowrisc PHY write: addr = 1, reg = 0, val = 0x200
get_prop_check_min_len: mac-address
get_prop_check_min_len: local-mac-address

My assumption therefore is that there is an issue with the Ethernet controller, but I might be missing something. Do you have any possible idea of what could be going wrong?