cva6

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When executing a simple test offloading a cvxif instruction (example: with core-v-verif, use the following command to execute cvxif_multi.S test; `python3 cva6.py --testlist=../tests/testlist_cvxif.yaml --test cvxif_multi --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=vcs-uvm`),...

ZElkacimi

[Bug Report] Issue with memory access

10

Hi, We found that cva6 allows LOAD instructions to load value from an address that is outside the DRAM space. According to RISC-V Unprivileged ISA V20190608, page 7, "if an...

chenc6

The readme instructs to ``` $ cd core/example_tb $ make veri_run ``` to run the core example testbench but there is no makefile in core/example_tb.

joeya20

### Is there an existing CVA6-SDK task for this? - [X] I have searched the existing task issues ### Task Description Build code to move Performance counter size to 64...

TulikaSi

[TASK] Raise a CQ (Eclipse contribution questionnaire)

1

### Is there an existing CVA6-SDK task for this? - [X] I have searched the existing task issues ### Task Description Raise the Eclipse contribution questionnaire. Guidance from @DBees might...

jquevremont

Failure to detect cache coherency violation.

2

Location: cva6/src/cache_subsystem (https://github.com/openhwgroup/cva6/tree/master/src/cache_subsystem). Details: According to the RISC-V specification, when the instruction memory is modified, the software should handle the cache coherency using FENCE.I instruction. If the input program modifies...

zarubaf

### Is there an existing CVA6-SDK task for this? - [X] I have searched the existing task issues ### Task Description NA ### Description of Done NA

RanjanThales

The boot program in the SD card cannot start the system

4

When I was performing the "Booting from an SD card" operation, I put the downloaded bbl.bin file into the SD card, and the output content when using FPGA for simulation...

2536786901

no makefile in core/example_tb

4

error while running following code from README.md: $ cd core/example_tb $ make veri_run

Rayz-b

error during make verilate

11

I'm getting the following error while doing make verilate on a fresh checkout of the repo: ``` ../corev_apu/tb/ariane_tb.cpp: In function ‘int main(int, char**)’: ../corev_apu/tb/ariane_tb.cpp:323:49: error: ‘class Variane_testharness’ has no member...

nFal