Add preliminary support for Nexys Video board

[xushengj]

This PR adds basic support for Digilent Nexys Video Artix-7 FPGA. The FPGA device is XC7A200T and is supported by Vivado WebPACK version.

Notable performance and functionality issues comparing with Genesys II:

1. Vanilla ariane core has a critical path delay of about 24-26 ns along FPU datapath on XC7A200T, and adding latency to FPU moves the critical path to integer data path with delay of about 23 ns. Therefore in this PR the clock is set to 40MHz and floating point instructions have 1-2 more cycles of latency.
2. Nexys Video board has only 512MB DDR3 memory.
3. Although Nexys Video board has identical RGMII interface for Ethernet, ariane-ethernet module keeps having timing violations and the ethernet just don't work.
4. (Needs help) After linux initialize the console, the baud rate somehow drops from 115200 to something near 108000. I haven't figured out what goes wrong. Any help is appreciated.

Major changes include:

1. Reorganized fpga/src/bootrom. Platform dependent sources are moved to subdirectories and Makefile will use $BOARD to choose one during bootrom generation. To generate the bootrom for Nexys Video board, run make clean && make all BOARD=nexys_video in fpga/src/bootrom.
2. Changed tcl script for xlnx_clk_gen to support Nexys Video board. The memory interface can at most run at 400MHz and the mig cannot generate 200MHz ui_clock, so a 200MHZ reference clock must be generated there.
3. New constraint file and SystemVerilog header for Nexys Video board.
4. Minor changes in rest of repository to account for this board.

[JeanRochCoulon]

As this PR is open since one year and a half. I would be pleased to status on it, and close it if nobody need this feature. @xushengj do you plan to merge it with the master branch ? @sjthales @jquevremont. Would you have any interest to support the Artix-7 FPGA ? Regards

[sjthales]

According to me, it should be interesting that cva6 be implemented on a more affordable board than Genesys2. The Nexys A7 (~250$) is quite interesting because it is a popular board. Arty7 (~100$) is another board also interesting, currently I don't know which board is the most interesting to be supported. Regards

[xushengj]

As this PR is open since one year and a half. I would be pleased to status on it, and close it if nobody need this feature. @xushengj do you plan to merge it with the master branch ? @sjthales @jquevremont. Would you have any interest to support the Artix-7 FPGA ? Regards

At that time I was not happy with the result I get (due to the problems I mentioned in the PR), and I had a Genesys 2 board for my project, so this PR is basically left there... The repo has changed a lot now and I think I will make another try when I'm available.

[JeanRochCoulon]

Glad to see you are working on the CVA6 again. As we can see from your PR comments, this PR would be appreciated because the FPGA you are targeting is inexpensive and different from GenesysII. So far I will add a distinctive tag to warm up your PR is pending

[xushengj]

@JeanRochCoulon I have rebased my changes in this PR. Most of the problems in my original message still exist. Anyway now the bitstream for Nexys Video board can be generated with make fpga BOARD=nexys_video. However, there are several important changes in the system:

• Clock speed for nexys_video is 25MHz instead of 50MHz. We get timing violations when targeting 50MHz.
• Although nexys_video have the same Ethernet PHY as genesys2, ariane-ethernet keeps having timing violations, so I disabled it
• UART cannot reliably work at 115200 bps so I changed it to 57600. If the rate is still 115200, the code in bootrom can print correctly but anything afterwards cannot.

Therefore we need to regenerate bootrom for Nexys Video board; the bootrom for Genesys2 won't work. I added a lot of parameters in bootrom generation; let me know if we have a place for documenting them.

The command I'm using to build bootrom: (in corev_apu/fpga/src/bootrom)

make bootrom_64.sv CLOCK_FREQUENCY=25000000 HALF_CLOCK_FREQUENCY=12500000 DRAM_SIZE_64=0x20000000 UART_BITRATE=57600 HAS_ETHERNET=0 PYTHON=python2

[JeanRochCoulon]

The last commit has broken the Github Action continuous integration !

[xushengj]

@JeanRochCoulon I think the errors were caused by the latest changes on the master branch. What I did was just rebasing my changes. Can you double check that?

[JeanRochCoulon]

@zchamski, As you can see, the regression does not pass anymore since the rebase has been done. Could you give to @xushengj the visibility on the Thales CI ? This will help to debug. Thanks

[zchamski]

Hi @xushengj , there is a publicly accessible CI for CVA6 with a broad spectrum of checks. You can access it at https://riscv-ci.pages.thales-invia.fr/dashboard/dashboard_cva6.html. By clicking on the PASS/FAIL button on the left-hand side of the CI pipelines you can access the status and summaries of individual jobs, which hopefully help you nailing down the regressions.

A new CI pipeline is triggered for every PR opened or updated on Github, so you can isolate (and analyze) the impact of each contribution.

More detailed instructions on how to access and use the dashboard are given here (they will land soon on the dashboard pages themselves.)

[JeanRochCoulon]

Hello @xushengj, unfortunately the PR cannot be merged anymore because the CVA6 code changed a lot since the PR has been submitted, November 2019. I propose to close it. Do not hesitate to submit again if possible. Sorry and thank for your interest.