Possible deadlock when executing from NI memory

[niwis]

This bug was initially reported in #708.

Consider the following scenario while executing from nonidempotent memory:

1. A branch instruction is fetched => speculative_d = 1'b1
2. The instruction queue is full, replay is asserted
3. Once the instruction queue is ready again, the frontend sends a request to the icache to refetch the branch instruction
4. The icache blocks as dreq.spec == 1'b1 (and we do not fetch speculatively from nonidempotent memory)
5. Deadlock

I think there are several possible ways to handle this, for instance:

• Clear the speculative register on a replay (proposed in #708)
• Disallow execution from NI memory (is this RISC-V compliant? Are there cases for executing from NI memory, e.g. the debug module?) Note: for the debug module, it might suffice to define only writes as non-idempotent and reads (including instruction fetches) as idempotent, which is possible according to the priv. spec but currently not supported by ariane.
• Allow speculative instruction fetches from NI memory, possibly violating the NI requirement
• Preventing replays in the first place when executing from NI memory, i.e. only fetching when the instruction queue can certainly accept an incoming instruction. For NI memory, we generally do not care about performance, and this might be the cleanest solution allowing to execute from NI memory without side effects.

I'm happy to help implement one of the solutions above (or yet another)!

[MikeOpenHWGroup]

Hi @niwis. I think this issue was resolved. Can you confirm? If so, please close this issue.

[niwis]

I don't think so. AFAIK one can still configure a memory region as executable and non-idempotent, and the core might still dead-lock if one does so.