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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Dear All, I have a question regarding the handling of the ECALL instruction (32h73): In the rvfi_tracer this instruction leads to the direct finish of the simulation (https://github.com/openhwgroup/cva6/blob/master/corev_apu/tb/rvfi_tracer.sv#L60). Can you...
Hello @Moschn and @zarubaf I am working on the write through cache you designed. I have some questions: - I would like to reduce the number of way to 2...
I tried to insert a new slave device (such as UART module) into the ariane soc by connecting them on cross bar ,however, the AXI crossbar becomes disabled after I...
Hi I am trying to use Dromajo to do HW/SW co simulation of cva6. As of now, I can simulate ariane with verilator simulator. Now I have to use Dromajo...
According to their respective User Manuals, both the CV32E40X and CV32E40S have adopted Version1.0.0-STABLE of the RISC-V Debug Support specification. As this has not yet been ratified by RISC-V International,...
I have a CVA6 hang that was discovered running random tests cases in an emulation environment. I am in email contact with Florian, and will send him simulation waveforms of...
In #602, there was a conversation like this: > Is the list of files in the manifest complete? >> Looks okay for the write-through cache version. Of course, the write-back...
> There is still work to do on sub-normalised divides but this is repeatable and unrelated. For example 2.350988561514729E-38 / 2 => 0. (it should give 1.175494350822288E-38, a subnormal value)...
Hello, I am trying to run the "make fpga" command after the successfull "make verilate" command and i'm getting this error : 1 Infos, 0 Warnings, 0 Critical Warnings and...
In `ariane_pkg.sv` parameter `MMU_PRESENT` is always set. It should not be the case since cv32a6_imac_sv0 configuration does not have MMU. https://github.com/openhwgroup/cva6/blob/e4b48a794b0229eeb9264a6b3f459c86545d1d85/core/include/ariane_pkg.sv#L625 I recommend to make this parameter depends on which...
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The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux