cva6
cva6 copied to clipboard
openhwgroup
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Let's say I have an execution of rdcycle (accessing the `cycle` register, addr 0xc00) in M-mode. if ((riscv::priv_lvl_t'(priv_lvl_o & csr_addr.csr_decode.priv_lvl) != csr_addr.csr_decode.priv_lvl)) begin privilege_violation = 1'b1; In this case `csr_addr.csr_decode.priv_lvl...
Hi I had raised a issue to lattice semiconductor regarding synthesis, They said : Are the only files in the script make the synthesis of cva6 core, As when they...
When I executed "make verilate DEBUG=1", I encounterd the following errors: ../tb/ariane_tb.cpp:113:10: error: ‘bool preload_aware_dtm_t::is_address_preloaded(addr_t, size_t)’ marked ‘override’, but does not override bool is_address_preloaded(addr_t taddr, size_t len) override { return...
Hi, I see this was discussed previously https://github.com/openhwgroup/cva6/pull/573 But I didn't find the interface in the design. Has it been implemented or not? Thank you!
I use the genesys2 development board, how to run my own program without operating system
As agreed in the meeting, these are the steps that you need to do, to be able to completely disable the data cache. Firstly : You need a parameter to...
I have tested systems generated with Chipyard on an FPGA (VCU118). With Rocket and Boom I also get plausible results here with Dhrystone and Coremark. However, with CVA6, the results...
Current, `mvendorid` reads as 0x0. I believe it should read as 0x0602 to match the vendor id of all other [CORE-V cores](https://cv32e40p.readthedocs.io/en/latest/control_status_registers/#machine-vendor-id-mvendorid).
I get: ```` Variane_testharness__Trace__2__Slow.cpp: In static member function ‘static void Variane_testharness::traceInitSub9(void*, VerilatedVcd*, const char*)’: Variane_testharness__Trace__2__Slow.cpp:3218:71: error: invalid conversion from ‘const char*’ to ‘int’ [-fpermissive] 3218 | tracep->declBus(c+24390,Verilated::catName(scopep,"BAUD_RATE"," "), false,-1, 31,0);...
hello, I encounter a problem when running Variane_testharness, I used the Verilator 4.104 and riscv64-unknown-elf-gcc (GCC) 9.2.0. I followed the instructions ```shell echo ' #include int main(int argc, char const...
Metadata
Owner
Metadata
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux