verilog-ethernet
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alexforencich
Verilog Ethernet components for FPGA implementation
@alexforencich @lomotos10
Hi! I am currently looking into cost effective solutions for transforming multiple input bit streams (datarate of 24*4bit*8MHz ~768 MBit/s) into UDP packages to send to a PC for storage/post-processing....
Hi, I am learning about how to set Vivado properties properly for CDC. When I looked down into the module 'axis_async_fifo', I didn't see any (* ASYNC_REG = "TRUE" *)...
Hi, Thank you for sharing your Ethernet/UDP/IP core. Just wonder if VLAN in the MAC layer is supported? Thanks
Hello, may I ask you a question? 40g is composed of four 10g channels. Referring to 802.3, we know that each channel adopts 64b / 66b coding standard. The axis...
[Vivado 12-180] No cells matched '.*/rx_sync_reg_[1234]_reg\[\d+\]'. ["F:/ExaNIC_X10/ExaNIC_X10.srcs/constrs_1/imports/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl":23] Maybe the second "_reg" should be removed?
Hello, I'm adapting AU50 design in my application and when I send packets with tcpreplay in the interface connected to the board with lower rates, the data is received correctly...
I tried with the exact same data stream, using 2 lfsr-modules with different DATA_WIDTH parameters (32 and 64) at the same time. I found the output is quite different.
The udp_checksum_gen_64 module drops a header when the header fifo becomes full. This happens due to ready latency in the header_fifo_ready path back to s_udp_hdr_ready. On the first clock cycle...
I try to port to VU440 but fail to make the project. My steps is as below. Please provide some advice. Thx. 1. Copy from project VCU108/fpga_1g to VU440/fpga_1g/ 2....
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Verilog Ethernet components for FPGA implementation