verilog-ethernet
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alexforencich
Verilog Ethernet components for FPGA implementation
Hey there, I'm new to working with FPGAs. I want to transfer Data from the IO's to the PC via Ethernet for that purpose I needed an Ethernet-Core and a...
I referenced the ExaNIC_X10 project and ported it to my own Ku060 board. Now, I have a problem where I downloaded the program to the board but the network card...
I made modifications directly from the ExaNIC_X10 project, only modifying the pin constraints and ref_clk constraints. I found that the project also couldn't run ，and phy was not connected. I...
https://github.com/alexforencich/verilog-ethernet/blob/master/rtl/axis_xgmii_tx_64.v#L174\ Should be reg [1:0]. I noticed this on a private unit simulation I did in Vivado XSIM with a Xilinx GTY. The truncation on [1] on this signal means...
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Verilog Ethernet components for FPGA implementation