verilog-ethernet
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alexforencich
Verilog Ethernet components for FPGA implementation
When udp_checksum_gen_64 is outputing a long packet (on m_udp_payload_axis_t...) , and enough 1-word packets are entering into this module (on s_udp_payload_axis_t...) so it fills up the header memory, the last...
Hello everyone and @alexforencich, I have a question about ARP mechanism in @alexforencich ethernet code. I have searched on the code but I could not get answer because of code...
This commit adds the Xilinx Kintex UltraScale+ KCU116 board featuring the XCKU5P-2FFVB676E FPGA and 4 zSFP cages. XGMII PHYs are instantiated for all four cages in `fpga.v` and passed down...
Porting KC705 example to Genesys2, the implementation has been inspired by pull request #6 and is compatible with the latest commits.
Here is a potential solution for the issue in #83. This adds a state to the SM to wait for the header commit to reflect in the FIFO before going...
Here's the first patch for the refactoring idea for corundum discussed here: https://groups.google.com/g/corundum-nic/c/ag28auMNfro/m/1MYs-kMJDgAJ It adds the `LAST_ENABLE` parameter that indicates whether the user gives the proper `last` signal. If this...
Hey @alexforencich, I just added support for one more board, can you merge it?
ARP sends a request 4 times with a 2 second delay then should wait for 30s before dropping packet. The parameter declarations and literals default to integer (signed 32 bit)....
Hi, I added an example for the Xilinx VC709 reference board based on the NetFPGA_SUME example. Hope you'll find it useful.
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Verilog Ethernet components for FPGA implementation