verilog-ethernet
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alexforencich
Verilog Ethernet components for FPGA implementation
PTP
May I ask how to add the PTP timestamp function in 10G Ethernet, I don't see the data adding port on the top layer.
Hi, To my understanding, this repo is now currently only for FPGA implementation, so I wonder if your team plans to target any ASIC implementation in the near future? Or...
Hi, I try to modify it an run it on VCU129 by modify VCU118 file. But i get failure in implementation phase.. Could you help to give us any idea...
Hello, I hope you are doing great. Thanks for the great IP. I am using your IP for implementing something on top of it and got in to a scenario...
In this module - **eth_mac_1g.v** - there are PTP signals ` module eth_mac_1g # /* * PTP */ input wire [TX_PTP_TS_WIDTH-1:0] tx_ptp_ts, input wire [RX_PTP_TS_WIDTH-1:0] rx_ptp_ts, output wire [TX_PTP_TS_WIDTH-1:0] tx_axis_ptp_ts,...
Hi, first of all, thanks for sharing your knowledge and give this IP. I'm currently doing my final project to obtain my Bachelor's Degree in Electronics Engineering and, as a...
Hello, First of all thank you for this great repo. I am trying to port this project to the UltraZed-EV card. For this I plan to use the SFP interface,...
Hello Alex, I'm using your library on a Xilinx Zynq (PL side) with a dual gigabit PHY. I use this both for UDP and RAW packets. No problem whatsoever. I'm...
Hi @alexforencich , First of all, thank you for sharing this wonderful library. I want to implement this project on Alveo U200 card. I follow verilog-ethernet/example/AU200/fpga_10g/README.md, run make to build,...
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Verilog Ethernet components for FPGA implementation