verilog-ethernet
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alexforencich
Verilog Ethernet components for FPGA implementation
- Converted some local parameter definitions into localparam's which reduces synthesis warnings. - Added missing port definitions in module instantiations - Fixed a typo in all sync_signal.v files located in...
According to [RFC1112](https://tools.ietf.org/html/rfc1112), addresses 224.0.0.0 – 239.255.255.255 (starting 0b1110) should be resolved by placing the low-order 23-bits of the IP address into the low-23 bits of the Ethernet multicast address...
Updated the RTL generate errors (labeling is missing at generate for loops)
I have added a Genesys2 board example, based on the Nexys Video example. By all means please merge with your version. Operation on the real hardware apparently succeeds with netcat....
The repo's already using `tox`, which is great, but it imposes some workstation/OS requirements which take some time to set up and may present an entry barrier for some. Proposing...
ZCU102 SoC part requires a Vivado license. This is the result from experimentation as reported at https://github.com/alexforencich/verilog-ethernet/issues/146#issuecomment-1429328609. To improve usability, this simply addition hints users to consider setting up the...
Digilent Genesys2 is quite a popular FPGA board with Xilinx Kintex-7 XC7K325T FPGA (the same as on Xilinx KC705). But Ethernet PHY on this board is Realtek RTL8211E-VL. The example...
Adds $rtoi before using COUNT_125US with $clog2. There may be other instances of this issue that I didn't encounter.
I am trying to set up an ethernet connection with Xilinks VCU 128, however the board is not responding. So, does the code in this repo for 118 VCU is...
hi, i'm trying use this project for 1 sfp channel. And my phy-layer not get up. there is i have some quations about ip(gtwizard): 1. If i create ip, i...
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Verilog Ethernet components for FPGA implementation