porting to VU440 with 88E1116

[Albert-Siu]

I try to port to VU440 but fail to make the project. My steps is as below. Please provide some advice. Thx.

1. Copy from project VCU108/fpga_1g to VU440/fpga_1g/
2. Type make to build the original VCU108 project
3. Modify device part number and pin assignment
4. Build the project again

I fail in step 2 which is make the project with the original VCU108/fpga_1g/. The error message is as below:

make all cd fpga && make make[1]: Entering directory /home/XXXX/project/fpga/eth/mod/verilog-ethernet-master/example/VU440/fpga_1g/fpga' make[1]: *** No rule to make target fpga.bit', needed by fpga'. Stop. make[1]: Leaving directory /home/XXXX/project/fpga/eth/mod/verilog-ethernet-master/example/VU440/fpga_1g/fpga' make: *** [fpga] Error 2

[alexforencich]

Sounds like a missing file or broken symlink. Does the VCU108 design build? Does your copy build, before making any modifications?

[Albert-Siu]

Yes. There are some symlink broken. I change to use KC705 example as a reference. As my PHY only support RGMII.

The next step is change device part number and pin assignment. Thx.