verilog-ethernet

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Is there any example for UDP stack + DHCP?

2

udp_complete.v works ok. Big thanks for nice udp stack implementation. Also, it would be great to have DHCP support in order to obtain IP address automatically from the router. Is...

qrp73

axis_fifo.v: odd behavior?

10

Hi Alex, while working on [Corundum Issue 122](https://github.com/corundum/corundum/issues/122), we (foremost @sessl3r, @andreasbraun90) have done a quick and dirty simulation of the `axis_fifo.v` using exactly the parametrization found in `mqnic_egress.v` and...

joft-mle

Query on configuring the ethernet for TX and RX operation???

1

Hi @alexforencich , I am trying to integarte one of your ethernet module (specifically eth_mac-10g_fifo) with my system on chip. In my SoC I have used the AXI4 as the...

dipal004

Cannot receive packets

4

I'm trying to use [ariane-ethernet](https://github.com/lowRISC/ariane-ethernet/tree/6a5436bf110f83ebb13119dbd82650ccd8f947c9) design in [OpenPiton+Ariane](https://github.com/PrincetonUniversity/openpiton) project, which is a Linux capable SoC design. There is no problem while compiling the RTL design and generating the bitstream (timing...

abdullahyildiz

UDP complete waves

10

Hey Alex, tks again for the IPs, bothering you again about usage! do you know how to get some waves of `udp_complete` module or if there's a diagram of how...

aignacio

Netcat doing nothing

13

Hi! So we were trying to implement your example on the alterra DE2-115 EP4CE115F29C7N board. The issue we are facing here, is that everything compiles nicely, the displays light up,...

surelynottrue

RGMII clk freq doubt

2

Hey @alexforencich, tks for the amazing repo, excuse my ignorance but if RGMII/1G requires a 125MHz clk tx/rx, why the tx data path uses 90MHz clk along with 125MHz@90degress offset?...

grey0skull

Illegal argument of type real in math function 'clog2()', expected integral type (Vivado 2022.1)

1

Hi, Running synthesis with Vivado 2022.1 I get the following error log: ``` WARNING: [Synth 8-9887] parameter declaration becomes local in 'ip_mux' with formal parameter declaration list [/source/path/rtl/ip_mux.v:118] ERROR: [Synth...

tux3

ICMP echo

3

Hi, thanks for this great project. I tried the UDP/IP stack with an ARRIA 10 SX (TERASIC HAN PILOT board) using quartus 21.1. All works good (UDP echo on port...

proconsule

Tx signals for raw ethernet frame

1

Hi Alex, I'm trying to modify `ip_eth_tx_64` to transmit raw ethernet frames. Since there's no IP header fields involved, how should the hdr_valid/ready signals to and fro `eth_axis_tx` be handled?...

dylanpjx