Error in ExaNIC_X10 example design timing constrain file eth_mac_fifo.tcl

[beyond2002]

[Vivado 12-180] No cells matched '.*/rx_sync_reg_[1234]_reg[\d+]'. ["F:/ExaNIC_X10/ExaNIC_X10.srcs/constrs_1/imports/fpga/lib/eth/syn/vivado/eth_mac_fifo.tcl":23]

Maybe the second "_reg" should be removed?

[alexforencich]

Constraints are correct; those signals were optimized out, hence the warning.