verilog-ethernet
verilog-ethernet copied to clipboard
alexforencich
Question about ASYNC_REG
Hi,
I am learning about how to set Vivado properties properly for CDC. When I looked down into the module 'axis_async_fifo', I didn't see any (* ASYNC_REG = "TRUE" *) attached to sync registers, and the tcl files under syn/vivado/ seemed not to set them either. Should I add the ASYNC_REGs myself or they are actually not necessary?
Thanks!
https://github.com/alexforencich/verilog-axis/blob/master/syn/vivado/axis_async_fifo.tcl#L67
You should also be able to verify that ASYNC_REG is set from looking at the implementation in Vivado. It should appear in the "properties" panel for the flip flops in question.
Is there any reason why SHREG_EXTRACTs are not set in tcl files just like how ASYNC_REG does?
Also, is SHREG_EXTRACT = "NO" needed for every synchronizer for Vivado? Although I might miss something again, but the rx/tx_rst_reg don't seem to be set either in RTL or in tcl files? Thank you!
SHREG_EXTRACT controls how the mapping works, ASYNC_REG is a placement constraint, so I decided to keep ASYNC_REG in the external constraints files. I'm actually not 100% sure if it's required, it's possible that setting ASYNC_REG will also prevent shift register inference. Mainly I do not want Vivado inferring SRL instances for the synchronizer chains, I actually want all of those discrete flip flops. I will take a look at that though, perhaps I can delete most of those SHREG_EXTRACTs.
Maybe creating a parameterizable CDC module for all the CDC code may also be a good idea (like the sync_reset module). By doing so all the Vivado properties can just be specified for one single file and we will not take the risk of missing any important properties.
True, I am considering doing something like that, but mainly have to sort out the logistics of where the files would be stored and the like.