verilog-ethernet
verilog-ethernet copied to clipboard
alexforencich
Verilog Ethernet components for FPGA implementation
I have implemented data loopback using your program. Now I want to parse the data sent by the upper computer, encapsulate it as the data packet that needs to be...
I'm highly interested in this project. However, I still need to connect my smartNIC to some legacy devices operating at 100M/1G speeds. It would greatly benefit me if this project...
Hi Alex , thanks for your Ethernet code.its really helpful for us in our project. Can you please provide micro architecture of Mac and mac control i.e. . svg file...
Dear Alex，thanks for sharing the codes which help me a lot. Is there any code for realizing 64B/66B to 256B/257B Transcoding in this repository?
Hi Alex, I am able to make zcu102 example project work for sfp0 on petalinux. Now i want to make new project in order to make it work for all...
Hi, Is there any Linux driver support for your Ethernet MAC? Thanks!
Hello and thank you for this repository! I am trying to understand how can I pack the Vivado Project into an IP, so I can use it with other projects....
Hi alex, I want to use your verilog project. I have edited your fpga.v and fpga_core.v files to use on my petalinux project. When i debug tx_tready signal by using...
Hi, Thank you for guide, I tested this code with ZCU111 and now I want to modify this code in "not loopback configuration" for that I follow this issue( #133...
I haven't simulated this; I have just been looking at your code to see if verilog-ethernet could be a compatible replacement for a similar, lesser version that I wrote and...
Metadata
Owner
Metadata
Verilog Ethernet components for FPGA implementation