alexforencich
support 40G
Hello, may I ask you a question? 40g is composed of four 10g channels. Referring to 802.3, we know that each channel adopts 64b / 66b coding standard. The axis stream output from Xilinx's MAC / PHY IP core is 256 bit wide. Where is the data merging of the four channels completed? Is it at the interface between the physical layer and the MAC layer
The merging is done in the PCS layer. See 802.3 section 82. It is far more complicated than 10G Ethernet. 40G Ethernet uses something called XLGMII between the MAC and the PHY, which is very similar to XGMII, except the packet start location is more restrictive, using 8 byte alignment instead of 4 byte alignment (64b/66b block types 2d, 33, 66 and 55 are not allowed) and the interface can be N*64 bits wide (incidentally, CGMII for 100G ethernet is exactly the same as XLGMII). I think 256 bit wide XLGMII is common. Then, the PCS layer handles striping the data across the four virtual lanes, inserting alignment markers, and transmitting the data. On the receive side, each physical lane has to detect the alignment markers, then they get remapped to the correct virtual lanes. Each lane has a FIFO that is used for deskew and there is a deskew routine to get that sorted out so all of the lanes are aligned.
As for 100G Ethernet, it's exactly the same as 40G Ethernet, except it uses 20 virtual lanes instead of 4 which are bit-muxed together and have independent gearboxes at the receiver. Additionally, a lot of 100G hardware also requires the use of RS-FEC. It's common for 100G MACs to use a 320 bit CGMII interface, as this maps into four 80 bit segments, which can each be split into five 16 bit segments. This works out nicely as each of the four physical lanes will carry five bit-muxed virtual lanes, so a static bit demux of 80 into 5x16 means that each of the 5 outputs will see a consistent virtual lane.
I have put some thought into this as I at one point was considering making a 10G/25G/40G/100G switchable MAC, but the 20 virtual lanes plus the requirement for RS-FEC at 100G basically resulted in that idea being put on hold indefinitely.
Thank you for your answer. I've seen the simulation file before. I'm still confused about the setting of the minimum 16 byte frame spacing. I wonder why you didn't set it to 12 bytes. Now I understand. Thank you again
The merging is done in the PCS layer. See 802.3 section 82. It is far more complicated than 10G Ethernet. 40G Ethernet uses something called XLGMII between the MAC and the PHY, which is very similar to XGMII, except the packet start location is more restrictive, using 8 byte alignment instead of 4 byte alignment (64b/66b block types 2d, 33, 66 and 55 are not allowed) and the interface can be N*64 bits wide (incidentally, CGMII for 100G ethernet is exactly the same as XLGMII). I think 256 bit wide XLGMII is common. Then, the PCS layer handles striping the data across the four virtual lanes, inserting alignment markers, and transmitting the data. On the receive side, each physical lane has to detect the alignment markers, then they get remapped to the correct virtual lanes. Each lane has a FIFO that is used for deskew and there is a deskew routine to get that sorted out so all of the lanes are aligned.
As for 100G Ethernet, it's exactly the same as 40G Ethernet, except it uses 20 virtual lanes instead of 4 which are bit-muxed together and have independent gearboxes at the receiver. Additionally, a lot of 100G hardware also requires the use of RS-FEC. It's common for 100G MACs to use a 320 bit CGMII interface, as this maps into four 80 bit segments, which can each be split into five 16 bit segments. This works out nicely as each of the four physical lanes will carry five bit-muxed virtual lanes, so a static bit demux of 80 into 5x16 means that each of the 5 outputs will see a consistent virtual lane.
I have put some thought into this as I at one point was considering making a 10G/25G/40G/100G switchable MAC, but the 20 virtual lanes plus the requirement for RS-FEC at 100G basically resulted in that idea being put on hold indefinitely.
So, do you have any plan to make this mac XLGMII compatible?
Not in the near future, unfortunately. Our focus is currently on either running links at 10G or 25G, or using hard logic for 100G links.
There seems to be an Apache 2.0 licensed 100G/50G/40G/25G/10Gbps MAC that was tested on VC709 development board. https://github.com/lewiz-support/LMAC_CORE3
