verilog-ethernet

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Does this 10G ethernet library use pause frames for flow control?

4

Thank you for sharing this wonderful library. Does this 10G ethernet library use **_pause frames_** for flow control?

myqlee

PHY MAC latency

1

I'm working on a project that will be intercepting and modifying TCP traffic as it crosses between the two ports on the Alveo U50DD. Now the functionality is working, I...

infamalex

Can this IP support 100G Ethernet?

1

ChomperT

There is no data return in ZCU106 example design

2

Hi Alex, I'm tring to start the ZCU106 example design ,I have successfully compiled the project and programed it to my board, but when I tested it with the command...

JLFu

NetFPGA_SUME for kintex ultrascale

2

Hi. I succses used this project with a little bit modifications for 10G ethernet kintex7. Now I want to apply ip ten_gig_pcs_pma_0.xci for ultrascale. The specification PG068 states that I...

SrodinW

I found a small bug in ssio_sdr_in_diff.v I don't know if you prefer a PR or an issue for small bug fixes. ``` diff --git a/rtl/ssio_sdr_in_diff.v b/rtl/ssio_sdr_in_diff.v index 7a0d7c1..fd05326 100644...

AlexLao512

I want to try the example for the DE2-115 board. The board is plugged into a FRITZ Repeater (the setup works great with other network devices). I edited the fpga_core.v...

Sch-Tim

Question - Verilog-Ethernet vs 1G/2.5G Ethernet Subsystem

2

I was wondering if this project could be used as a replacement for the Ethernet subsystem provided by Xilinx in Vivado. The Subsystem holds a MAC, Ethernet Buffer and PCS/PMA...

Beauxrel

I'm trying to get better at verilog and i saw the project coding style and i get a little confused. The FSMs are in the Mealy method but outputs updated...

danieldanino17

1G RGMII on KR260

12

Hello, First off I just want to say thank you for making this resource available, it's a significant enabler for so many projects - thank you. The issue I am...

russell-t