verilog-ethernet
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alexforencich
Verilog Ethernet components for FPGA implementation
well, i 'm a newcomer.i have successfully make the vivado project,but what should i do next to program it onto U50?do i need to make a mcs and then program...
Is KC705 full duplex? Because the light of the duplex of my development board is on
When USE_CLK90 == "TRUE", phy_rgmii_tx_clk register has very tight timing on the data path: clk90 - clk = 2ns. Vivado often fails to meet this timing on Artix-7 FPGA. I...
Hi, I'm trying to create network tap with aggregation support, your code was great help for me since I recently started working with FPGA and even though I don't understand...
Hi Alex, Wanted to check a few things with regards to the MAC around a specific topic with regards to runt packets. 1. Is there any possibility that the MAC...
The LFSR module (eth_crc_8 instance) is producing warnings and not synthesizing correctly in both Mentor Precision and Synopsys Synplify Pro tools. Both tools in the RTL view show that data_in...
I've been experiencing issues with a modified version of the VCU108/VCU118 designs (all of the modifications were made after the udp_complete module to add packet types, nothing about the PCS/PMA...
Hello, I'm using the Broadcom® B50610 triple-speed PHY chip, and I'd like the FPGA run as MAC controller to communicate with the PHY chip. I was wondering whether verilog-ethernet supports...
Thanks for this IP! However, I have a small issue. I'm trying to figure out exactly what signals are needed to produce just a single UDP TX packet, but I...
I may be doing something dreadfully wrong but I'm getting about half the expected data rates for the 10G and 25G QSFP Ethernet examples. (its okay, even half rate is...
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Verilog Ethernet components for FPGA implementation