verilog-ethernet
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alexforencich
Verilog Ethernet components for FPGA implementation
hello I built the project and the .bit is built correctly but when I test on the board unfortunately the ARP packets are not responded to correctly. As shown in...
Hello! I am currently testing the stability of the project, especially the compatibility with hardware operations during device runtime. I noticed that in real-world scenarios, it is possible that optical...
https://github.com/chili-chips-ba/wireguard-fpga/issues/14#issue-2879563883
Thanks for this super nice project! Does this Ethernet project include Auto-Negotiation? I looked at the RTL file name and there seems to be no such module.
I had earlier targeted the verilog-ethernet design on Alveo u50 and it worked as expected during testing. I would now want to understand and explore the Alveo X3522 card and...
Modified the project to be compatible with AX7203 ARTIX 7 FPGA - xc7a200tfbg484 -2 part. It has been tested in board as well using both hping and netcat.
Hi, I'm trying to build a example project for KC705. I get an error: "No rule to make target '../lib/eth/rtl/oddr.v', needed by 'update_config.tcl'. Stop." What am I doing wrong? Full...
Many SPI to MII conversions are used on microcontrollers, but there is a lack of FPGA implementation on the entire GitHub. The difficulty of implementation mainly lies in compatibility with...
Hello, I hope this message finds you well. I have noticed that the ptp_clock module does not support negative increments (using two's complement) when adjusting the clock with input_adj_ related...
Forgive me if this information is posted elsewhere but what is the process for commiting addition platform support? I was recently able to leverage the KC705 Example design to successfully...
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Verilog Ethernet components for FPGA implementation