VexRiscv
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SpinalHDL
A FPGA friendly 32 bit RISC-V CPU implementation
Hi guys - I have firmware written in rice and read and write data on HBM, - currently, I can read and write data 4 bytes at a time, however,...
Hi Can you give me a passed operation on it. Thanks a lot Sent from PPHub
Hi, I am having an issue with simulating the correct behavior in modelsim. It's possible that this is due to some configuration issue. Two issues I have noted. 1. AUIPC...
I see that it is possible to change the PC value in the custom instruction under [here](https://github.com/SpinalHDL/VexRiscv#add-a-custom-instruction-to-the-cpu-via-the-plugin-system) How can I do this?
Hi, I have the scala code which is working well and meet my demand. However, I am wanting to increase the address space from 32 bits to 64 bits. Can...
Seems Vexriscv by default has a 'simple' Ibus/Dbus implementation to fetch instructions and read/write data. What are the semantics of this bus? It seems AXI-like, but I cannot really find...
Hello, recently I have been wanting to add an SPI peripheral IP with a standard AXI structure to Briey's AxiCrossBar, which is written in SystemVerilog. I have noticed that the...
I need to change a reg reset kind to SYNC in vex core. So, I try to implement by using ClockDomain object according to SpinalHDL docs. val decodePc_Domain = ClockDomain(ClockDomain.current.readClockWire,ClockDomain.current.readResetWire,...
Apologies for the naive question, but how do I run a cycle-accurate Verilator simulation of a simple C program, run it on the VexRisc processor RTL and calculate how many...
Hi, Is there a way to exit the verilator simulation from the C code whose hex is getting executed using RUN_HEX. For some reason, certain C codes are exiting but...
