VexRiscv
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SpinalHDL
A FPGA friendly 32 bit RISC-V CPU implementation
Hi... I am trying to execute this code, . . . void print(const char*str){ while(*str){ uart_write(UART,*str); str++; } } void println(const char*str){ print(str); uart_write(UART,'\n'); } void delay(uint32_t loops){ for(int i=0;iOUTPUT;...
Hi, I follow the README to config/build/run verilator simulation for Briey SoC. The VGA window prompted. However, it displays nothing, terminal print 2 lines below then no output any more....
So, this is a pretty big challenge I think.... The iCE40 1K has the following resources; * 1280 Logic Cells * 64kbits Embedded RAM bits * 1 PLL However, there...
Makefile -> SIFIVE_GCC_PACK = no #then export PATH=$PATH:/opt/riscv32i/bin export AR=riscv32-unknown-elf-ar export AS=riscv32-unknown-elf-as export CC=riscv32-unknown-elf-gcc export CXX=riscv32-unknown-elf-g++ export LD=riscv32-unknown-elf-ld cd $HOME/icesugar/icesugar/src/advanced/VexRiscv/src/main/c/murax/hello_world make 1, can the the hex fit for ice40-Hx8K? that...
Hi, I found out a few things about ["modified" Briey SoC](https://github.com/jmio/ECP5_Brieysoc/tree/dev) not working on the actual device (ECP5, ICESugarPro). For "non-booting" FPGAs with dev-dev bit files wrote: + OpenOCD can...
https://www.embench.org/ > Dhrystone and Coremark have been the defacto standard microcontroller benchmark suites for the last thirty years, but these benchmarks no longer reflect the needs of modern embedded systems....
[avalon_qsys_sdram_16bit_errors.zip](https://github.com/SpinalHDL/VexRiscv/files/7109498/avalon_qsys_sdram_16bit_errors.zip) Here a Quartus 18.1 project project including the signaltap_avalon_sdram_16bit_error.stp signaltap records. Theoretically if you open the project with File view, you can double-click on the signaltap file, and it...
Hey, I build myself a vexriscv core on my arty and im trying to figure out how the DRAM addressing exactly works. When i use "sdram_force_wrphase 0x4FFFFFFF" i would expect...
It would be nice if VexRiscv had support for vectored interrupts. Basically something like fast interrupts in [Ibex](https://ibex-core.readthedocs.io/en/latest/exception_interrupts.html).
Hi Where is official tutorial to burn Vex to Artix 7? Any tutorial to burn it to other xilinx board too? thanks Peter
