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Published 20 hours ago • verified publisher icon SpinalHDL

Documentation for 'simple' ibus/dbus protocol missing

Open Spritetm opened this issue 1 year ago • 2 comments

Seems Vexriscv by default has a 'simple' Ibus/Dbus implementation to fetch instructions and read/write data. What are the semantics of this bus? It seems AXI-like, but I cannot really find any details anywhere.

Spritetm avatar Sep 25 '22 08:09 Spritetm