VexRiscv
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How to configure AXI address space more than 32 bits
Hi,
I have the scala code which is working well and meet my demand. However, I am wanting to increase the address space from 32 bits to 64 bits. Can you please help me to do that?
https://www.file.io/IPgo/download/7CdYWSaBpnSM Here is the file
Thank you, Duc