VexRiscv
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SpinalHDL
A FPGA friendly 32 bit RISC-V CPU implementation
Hi, first of all congratulations for your impressive work. I'm currently evaluating different RISC-V cores and VexRiscv is my favourite so far. I have a problem when trying to configure...
Supporting TCM, similar to ARM cores, would be a good alternative to caches. It should be a bit less resource-hungry, it's more deterministic for hard real-time applications, and we can...
See https://github.com/mupq/pqriscv-vexriscv > The goal of this project is to implement a simple test-platform for the VexRiscv CPU, to be used as a reference platform for benchmarking and experimenting with...
I've been playing around with RiscVexV for use as an embedded FPGA processor. The ```DBusSimplePlugin``` supports LR/SC but not AMO instructions to enable the full "A" extension. Are there plans...
I'm trying to use VexRiscv with Zephyr, but it generates an illegal instruction exception when trying to call the z_arch_irq_enable function. I could debug it, and this is the instruction...
VexRISC-V uses blockrams on the iCE40. This should make it easy to support saving the whole register file by changing one of the upper address bits. This would be super...
I just want to report some unused flip-flop registers. They got removed during elaboration and since they are never used, they could also be removed? We should discuss how to...
Hello all, I'm having a little problem with the FPGA implementation to test functionality on sillicon and the compilation is completely fine but when it comes to interfacing with the...
VexRiscv implements a simple MMU. This MMU is effective, but nonstandard, and requires extended instructions to do refilling. Would it be possible to give a simple example of how to...
This change add an additional memory to the pipeline for those cases where maximum clock is speed is required and data RAM latency is 2. Right now, you can already...
