VexRiscv
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SpinalHDL
A FPGA friendly 32 bit RISC-V CPU implementation
Hi, I intend to test some of the softwares provided for Briey on the DE0 Nano SoC. I first ran the TCL scripts as explained by the readme in the...
https://gcc.gnu.org/onlinedocs/gccint/Processor-pipeline-description.html#Processor-pipeline-description Add something like: https://github.com/gcc-mirror/gcc/commit/8b1090c1eaf28580aeac2de46401eaf4fc91bb5a for VexRiscV
The MulPlugin, DivPlugin, and MulDivIterativePlugin all require that `withWriteBackStage = true` and `withMemoryStage = true`. This can make it difficult to shrink the core, especially since the MulPlugin ought to...
Aloha! Noticed that the name of a directory in VexRiscv/src/main is "ressource". Is that a spelling error?
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This is the first RISCV core I've been able to get up and running without breaking my head. Much appreciation for the SpinalHDL team for the making this work with...
:tada: https://twitter.com/risc_v/status/1070389876900679680
After a discussion with @Dolu1990 , it was revealed that 50% of the gate count of a minimal VexRiscv is the register file, which is 32x32-bits. That's many registers. The...
File name: GenSmallAndPerformant.scala Module name: GenSmallAndProductive Same thing for: GenSmallAndProductiveWithICache Which is the right name: *performant or *productive? Once I know, I'll submit a patch. Tom
When I run the riscv-formal testsuite, the branch instructions are all failing. Branches to locations for which bit [1] is set are expected to result in a trap, but they...
Awesome project! I am trying to add custom SIMD instructions. Is it possible to add 48 / 64 bit instructions? Can `iBus_rsp_inst` bus be extended to 64 / 128?