VexRiscv
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SpinalHDL
A FPGA friendly 32 bit RISC-V CPU implementation
Both settings should be enabled by default in all configurations, and the possibility of disabling it should be deprecated. The reason is that compilers rely on the correct trapping behavior...
We've been evaluating using VexRiscv for a project, and it's mostly been going beautifully. Even though nobody on our team knows Scala super well, VexRiscv and SpinalHDL so far is...
Hi all I create an empty project using Lattice diamond and paste the Briey.v to it. I got this error while synthesis, please help. ERROR - c:/workspace/fpga/tryvexcore/briey.v(4009): system function call...
Hi my openocd missing jtag_tcp.cfg, where is this file? thanks Peter
I have followed to https://github.com/SpinalHDL/VexRiscv/tree/master/doc/nativeJtag, but I need to modify for my Altera DE0-Nano-SoC board (Cyclone® V SE 5CSEMA4U23C6N device) and Altera Virtual JTAG. Unfortunately, it was not successful yet....
Hello, I'm working on getting started with VexRiscv. I can successfully run Briey and interact with it via OpenOCD and GDB. However, in trying to build some automation tools, I've...
I tried to set the `assertIllegalInstruction` option of `DecoderSimplePlugin` and my simulation instantly failed although it shouldn't. Looking at the wave trace, this already happens in the first cycle after...
Are there any changes that are to be made to Crt.s file as here I am not getting any output displayed. The code runs well on any c compiler but...
As far as I can tell (and as far as I tried), compiling with Scala 2.13 is not supported.
Hello, I am currently trying to generate linux image to simulate linux booting on VexRiscv. To do so, I follows guidelines in src/main/scala/vexriscv/demo/Linux.scala: ``` Buildroot => git clone https://github.com/SpinalHDL/buildroot.git -b...
