softcore topic
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
80x86
80186 compatible SystemVerilog CPU core and FPGA reference design
USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC,包含一个简单且可扩展的外设总线。
forth-cpu
A Forth CPU and System on a Chip, based on the J1, written in VHDL
tree-core-cpu
:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and v...
risc8
Mostly AVR compatible FPGA soft-core