softcore topic

A FPGA friendly 32 bit RISC-V CPU implementation

SpinalHDL

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

darklife

80186 compatible SystemVerilog CPU core and FPGA reference design

jamieiles

An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。

WangXuan95

A Forth CPU and System on a Chip, based on the J1, written in VHDL

howerj

:deciduous_tree: A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and v...

microdynamics-cpu

Mostly AVR compatible FPGA soft-core

osresearch