AxiCrossBar with Standard Axi4 Interface in Briey

[ic-hjx]

Hello, recently I have been wanting to add an SPI peripheral IP with a standard AXI structure to Briey's AxiCrossBar, which is written in SystemVerilog. I have noticed that the Axi4Shared interface is predominantly used in Briey's AxiCrossBar, and I believe the AxiCrossBar should be able to support the use of both the Axi4 standard interface and the Axi4Shared interface simultaneously. The main issue I have encountered is that I do not know how to use the function addPipelining on an object of the Axi4 standard interface, and I have not found any relevant examples so far.

def addPipelining(axi: Axi4)(ro: (Axi4ReadOnly, Axi4ReadOnly) => Unit)(wo: (Axi4WriteOnly, Axi4WriteOnly) => Unit): this.type = {
  val b = axi4SlaveToReadWriteOnly(axi)
  val rAxi = b(0).asInstanceOf[Axi4ReadOnly]
  val wAxi = b(1).asInstanceOf[Axi4WriteOnly]
  addPipelining(rAxi)(ro)
  addPipelining(wAxi)(wo)
  this
}

Regarding the AxiShared interface, I can see that the function is used as follows:

axiCrossbar.addPipelining(ram.io.axi)((crossbar, ctrl) => {
  crossbar.sharedCmd.halfPipe()  >>  ctrl.sharedCmd
  crossbar.writeData            >/-> ctrl.writeData
  crossbar.writeRsp              <<  ctrl.writeRsp
  crossbar.readRsp               <<  ctrl.readRsp
})

However, for the Axi4 type interface, I am not quite clear on how to wire it, so I am seeking some assistance and looking forward to your reply!