VexRiscv
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SpinalHDL
A FPGA friendly 32 bit RISC-V CPU implementation
## Summary After adding `EmbeddedRiscvJtag` to a VexRiscv design as described in the README, I was not able to connect to it. I'm using yosys/nextpnr to target an ECP5, I...
I wanted to ask if VexRiscv would support the RISC-V vector extensions sometime in the future. Thanks!
while compiling verilog code ( .v), i get following errors.. can you please tell me where is error either of generated code from scala to verilog (by sbt "runMain vexriscv.demo.Murax"...
Since I need them for a project, I was wondering, if the performance counters will be implemented. I might try building them myself, but I feel not as familiar with...
Currently I am working on a project that is based on the Murax SoC. At this moment I am focused on the function of interrupts. Is there any documentation on...
There is a logic bug in the following code. ```scala //Build spec val spec = encodings.map { case (key, values) => var decodedValue = defaultValue var decodedCare = defaultCare for...
hello tried to simulate vexriscv followed the instructions from Linux.scala the linux files are VexRiscvRegressionData/sim/linux laur@laurPC-100:~/lucru/cn/riscv/vexriscv-linux/VexRiscv/src/test/cpp/regression$ verilator --version Verilator 5.002 2022-10-29 rev v5.002-29-gdb39d70c7 export BUILDROOT=/home/laur/lucru/cn/riscv/vexriscv-linux/buildroot laur@laurPC-100:~/lucru/cn/riscv/vexriscv-linux/VexRiscv/src/test/cpp/regression$ make clean run IBUS=CACHED...
Currently I am developing against a local SpinalHDL `dev` branch, along with local VexRiscv `dev` and the VexRiscv-specific latest OpenOCD (i.e. using the "old" VexRiscv debug module") and I am...
Hi, I would like to use a memory on the apb bus. How can I use this part of Murax Soc to use a ROM on the apb bus? ```...
