VexRiscv
VexRiscv copied to clipboard
SpinalHDL
A FPGA friendly 32 bit RISC-V CPU implementation
Hello, I'm extending a coprocessor instruction and defining a coprocessor interface like ROCC, but I don't know how to have access to the memory and read some data. Should I...
This PR will add the documentation for the VexRiscv project: DO NOT MERGE UNTIL: - [ ] Add tag base versioning to sphinx - [ ] Set up Travis CI...
Set up SpinalSim and Verilator according to https://spinalhdl.github.io/SpinalDoc/spinal/sim/introduction/#performance. Got this error [sim_log.txt](https://github.com/SpinalHDL/VexRiscv/files/4293968/sim_log.txt) after sbt "test:runMain vexriscv.MuraxSim"
Hello, I am new with both SpinalHDL and RISC-V. I have compiled Murax Soc using internal RAM on Arty7 and they work well. Now I want to use external SDRAM...
Hi, I am having an issue with Vivado implementing a large number of BRAMs in the DCache. It appears that each byte in the cache is being implemented as an...
A new `CsrPluginConfig` that generates only M and U mode was included with the new PMP plugin. https://github.com/SpinalHDL/VexRiscv/blob/d2855fcfca5410c6986b0c3e816cbb867e9b22b9/src/main/scala/vexriscv/plugin/CsrPlugin.scala#L267 This is used to instantiate a new core called `VexRiscv_Secure` in the...
use the Vexriscv,and generate the MuraxSOC(InitRam).running on FPGA board, the UART and GPIO(Blink led) are working. when I use the openocd connect the core, "Error: dtmcontrol is 0. Check JTAG...
hi, i notice that when adding a user-defined interrupt using UserInterruptPlugin, it just use the `interruptPending` as the cond signal ,without any enable signal as a gate controller https://github.com/SpinalHDL/VexRiscv/blob/98de02051e1a5c9400c022dc61acd4bd0507f8a5/src/main/scala/vexriscv/plugin/CsrPlugin.scala#L1153-L1155 it...
Hi, I notice that in the smp branch, the VexRiscv supports larger memory data width (e.g., 128 bits) which is bigger than the cpu data width (32 bits). However, in...
