VexRiscv

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AXI IO interface with VexRISCV SMP

3

Hello, I'm looking to generate the Verilog/Vhdl of a VexRISCV multicore SMP processor but rework its IO buto AXI. I see it has been done for a single VexRISCV core:...

goodwilj

data cache stuck

3

Hi Dolu1990, Found a weird D-cache stuck issue. Attached the waveform. It's related to refilling. D-cache goes into line fill phase and expect loader_counter_values to go up. On the other...

hchoi-lattice

[Question] How can I run C code on vexRiscv?

3

Hey, I have generated the Full version of vexRiscv using `sbt "runMain vexriscv.demo.GenFull" ` and then I ran some regression tests which passed. I tried running the uart.elf example using...

adz0612

Data Stream in/out SoC <-> FPGA

6

Hello, I'm building a softcore based on Briey. I've the AxiCrossbar without Sdram and on the APB3Bridge 1 Timer, 1 UartCtrl, 1 Gpio. On the APB3 I would like to...

lk-davidegironi

Instructions to save/restore register to stack is taking 2 clock each

12

I wrote a simple task switching that save registers and restore registers // Save registers sw s0,4(sp) sw s1,8(sp) sw s2,12(sp) sw s3,16(sp) : : // Restore registers lw s0,4(sp)...

ztachip

DE0-Nano Board with VexRiscV: IO and Fit Design Issues Including Specific Command Used

3

Hello VexRiscV Community, I've been trying to run my VexRiscV project on my DE0-Nano FPGA board and encountered two issues. I aimed to configure the project for a Cyclone IV...

Tahamermer

Perf counters

3

Fixes #361 Not tested, because I did not find the time for it. So I do not know, whether it works or not.

jjjt-git

Murax XIP compile issue

11

Hello, I'm trying the Murax soc on a Tang Nano 9k. MuraxWithRamInit works with no issues. I'm able to run the demo, and to compile custom C software. Now I...

lk-davidegironi

Fetch dosen't performed correctly in the simulation of Murax SOC.(+Custom instructions are executed in unexpected time.)

1

Hi there! I appreciate your involvement in this project. I'm developing a plugin to add shadow stack functionality to VexRiscv. I've implemented instructions, 'sspush' for pushing onto the shadow stack...

nohahanon

debug

1

Sent from PPHub

chshux