VexRiscv
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A FPGA friendly 32 bit RISC-V CPU implementation
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The EU has €270 million in funds for Risc-V projects. https://www.hpcwire.com/2022/12/16/europe-to-dish-out-e270-million-to-build-risc-v-hardware-and-software/ We should figure out how to get some of that money. Presumably people here are already working on that....
I try to create a custom instruction for fast context switching The opcode will save a register value and at the same time restore the register to last saved value....