core-v-verif
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openhwgroup
Functional verification project for the CORE-V family of RISC-V cores.
@silabs-hfegran @silabs-mateilga I am currently looking at the transition to using ImperasDV, and I wanted to get a baseline set of results. I checked out the CV32E40X/dev branch, and when...
## PUSH and POP type instructions marked as illegal instructions ### Type * Functionally incorrect behavior ### Steps to Reproduce 1. Use my fork of core-v-verif: [email protected]:silabs-oysteink/core-v-verif.git 2. Checkout my...
### Is there an existing core-v-verif task for this? - [X] I have searched the existing task issues ### Task Description We have to implement a process to control the...
Added Simulation stop scenario and outputs signals tests_passed, tests_failed, exit_value, exit_valid to **cva6_tb.sv** and **cva6_core_tb_sram.sv**
Hi All, I have an issue with cebreak tests while running in cva6 core for riscv-arch-test suite, it has some gpr mismatch between spike and verilator as shown below. [cebreak.S](https://github.com/riscv-non-isa/riscv-arch-test/blob/main/riscv-test-suite/rv32i_m/C/src/cebreak-01.S)...
@JeanRochCoulon I saw a new tool has been created called vptool. I followed the instructions in VPTOOL-readme.txt for installation of packages, then whent to the vptool-example directory trying to run...
Is the necessary steps required to use CLIC interrupts with the ISS documented anywhere? I presume there will be some new nets that needs to be interfaced with the test...
### Is there an existing core-v-verif task for this? - [X] I have searched the existing task issues ### Task Description Provide VPTOOL to edit the verification plan VPTOOL windows...
SVAs for checking user-mode, according to the vplan https://github.com/openhwgroup/core-v-verif/issues/1256. Note, rtl is not ready to pass everything yet, and rvfi updates are needed. (But our test stimuli doesn't exercise user-mode...
cv32e40s_csr_template.yaml was updated in #1328, this issue serves as a remainder to generate a new test-section for the csr_access_test. (Test is automatically generated with some minor hand-modified sections)
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Functional verification project for the CORE-V family of RISC-V cores.