core-v-verif
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openhwgroup
Functional verification project for the CORE-V family of RISC-V cores.
As requested by @MikeOpenHWGroup in #2386, here is a refactoring of tb_ifs file. Since CV32E40Pv2 is close to the release date as pointed out in #2386 discussion, I leave that...
Hello, the [cv32a65x spec](https://docs.openhwgroup.org/projects/cva6-user-manual/06_cv32a65x_riscv/index.html#virt-control) the TW filed in MSTATUS is read-only zero, but Spike allow the read 1 in TW filed after a write into it in both modes TANDEM...
Hello, in the CV32A65X configuration the mtval is read-only zero (doesn't not raise an exception if we write into it), is means we only have the zero value in it,...
As per issue #1933 , I have modified `run_phase` to `main_phase` to be in consistent with the use of other run time phases (`reset_phase`, `confgure_phase`) in the base test, firmware...
### Type * Other. ### Steps to Reproduce `cd vendor`. If you don't already know what that directory is, you won't find out in that directory. Is it documented in...
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Functional verification project for the CORE-V family of RISC-V cores.