core-v-verif
core-v-verif copied to clipboard
openhwgroup
Added VP details to cva6_tb.sv and cva6_core_tb_sram.sv
Added Simulation stop scenario and outputs signals tests_passed, tests_failed, exit_value, exit_valid to cva6_tb.sv and cva6_core_tb_sram.sv
Hello @RanjanThales, it seems good. Do you have run the Thales CI on this PR ?
Hello @RanjanThales, it seems good. Do you have run the Thales CI on this PR ? I am having some Microsoft authentication issue , not able to open https://gitlab.thalesdigital.io/ (In discussion with IT team to resolve this) However, i have performed a simulation with repo cva6/dev (locally), its seems previous compilation issue has been resolved now.
Hi Mike, Simulation wise no issue in my local machine, however, we have some issue with CI flow (what yannik has presented), i.e. inherited variables in the downstream variable have a lower priority than the project variable , so its not picking up correct one. We are looking some other workaround on this.
Thanks @RanjanThales.
@JeanRochCoulon, @ASintzoff, @RanjanThales: I have added a "DO NOT MERGE" label to this pull-request until the CI issue has been resolved.
@JeanRochCoulon, you will probably be the Committer who approves and merges this one - when you are ready to do this please remove the label beforehand - thanks!
Hi @RanjanThales, @JeanRochCoulon, @ASintzoff, this PR is now rather old. What is it's status?
Hi Mike, The correct CI run for this merge is reported previously( https://gitlab.thalesdigital.io/riscv/core-v-verif/-/pipelines/1307923), however later the corresponding files are removed (cva6_tb.sv, cva6_core_tb_sram.sv), making this as conflicting files for merge.
Hi @RanjanThales , @zchamski is implementing a test termination based on htip protocol. In that way the termination will be the same between Spike and RTL. It has been presented last CVA6 meeting by @zchamski, the slides are available on Mattermost. Please give us your feedback to confirm the htif method will cover the feature you were implemented with the current PR.
Hi Mike, The correct CI run for this merge is reported previously( https://gitlab.thalesdigital.io/riscv/core-v-verif/-/pipelines/1307923), however later the corresponding files are removed (cva6_tb.sv, cva6_core_tb_sram.sv), making this as conflicting files for merge.
@RanjanThales, are you saying that the Thales GitLab version of core-v-verif and the OpenHW GitHub version are out-of-sync?
Hi Mike, The correct CI run for this merge is reported previously( https://gitlab.thalesdigital.io/riscv/core-v-verif/-/pipelines/1307923), however later the corresponding files are removed (cva6_tb.sv, cva6_core_tb_sram.sv), making this as conflicting files for merge.
@RanjanThales, are you saying that the Thales GitLab version of core-v-verif and the OpenHW GitHub version are out-of-sync?
No, @MikeOpenHWGroup, I don't mean both the core-v-verif are out-of-sync (both are same), however, somehow the following files cva6/tb/core/cva6_tb.sv cva6/tb/core/tb_components/cva6_core_tb_sram.sv are removed in earlier commit.
Unfortunately this PR is out of date. No way to synchronize with the current database. @RanjanThales could you confirm I can close it?
Yes @JeanRochCoulon, I couldn't get much on htip protocol, may be going forward we can replicate the same implementation with new PR, you can close this PR for now. Thanks, Ranjan.
Thanks @RanjanThales. Also if the PR is close, it is logged by GitHub. It is not lost.