core-v-verif

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Test: working with issues

2

Hi Joe and Maarten, this issue is a test of the following: 1. A check to see if I can assign an issue to you (I can). 2. A check...

MikeOpenHWGroup

[TASK] Dashboard for CVA6 regression based on core-v-verif

3

### Is there an existing core-v-verif task for this? - [X] I have searched the existing task issues ### Task Description Provide a way to have regression status when contributors...

yanicasa

OVPSIM mret does not set MIE = MPIE in MSTATUS CSR

70

For a few select seeds when running the "corev_rand_interrupt_wfi_mem_stress" test, what seems to be a bug in the reference model can be observed. The scenario is that when a core...

silabs-mateilga

Add comparison of RVVI/RVFI sleep signals in step and compare

1

### Task Outcome Two new comparable "sleep" signals are being implemented in RVFI and from the RVVI. These need to be compared in the step-and-compare scoreboard ### Completion Criteria A...

silabs-mateilga

CVA6 arch tests are failing with latest riscof environment

7

### Issue Description HI In latest RISCOF CVA6 riscv-arch-tests tests are failing due to mismatch in between spike and verilator csv. I used [cva6_spike_log_to_trace_csv.py](https://github.com/10x-Engineers/core-v-verif/blob/8fc3143c3c14973e123bdb52a6c92f1ce9b1f115/cva6/sim/cva6_spike_log_to_trace_csv.py) script for spike log to csv...

spidugu444

[TASK] CV-X-IF CVA6 verification

3

### Is there an existing core-v-verif task for this? - [X] I have searched the existing task issues ### Task Description Run randomly generated tests by core-dv (riscv-dv) using custom...

ASintzoff

PMP vplan review, cv32e40s

4

### Task Outcome The attached 40s vplan for PMP is reviewed, revised, accepted, and pushed to the repo. ### Location Information The spreadsheet is uploaded in this PR: https://github.com/openhwgroup/core-v-verif/pull/1288. ~~The...

silabs-robin

User-mode vplan review, cv32e40s

5

### Task Outcome The attached 40s vplan for user-mode is reviewed, revised, accepted, and pushed to the repo. ### Location Information The spreadsheet is uploaded in this PR: https://github.com/openhwgroup/core-v-verif/pull/1287. ~~The...

silabs-robin

### Is there an existing core-v-verif task for this? - [X] I have searched the existing task issues ### Task Description UVM agent behaving as a coprocessor with dedicated custom...

ASintzoff

[TASK] Add riscv-arch-test suite to existing CVA6 core-v-verif CI (32-bit and 64-bit)

1

### Is there an existing core-v-verif task for this? - [X] I have searched the existing task issues ### Task Description Adding riscv-arch-test suite for riscv cva6 environment. Steps: 1.Please...

spidugu444