core-v-verif

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### Task Outcome A target for isacov features and cleanness is set, and a target for test stimuli comprehensiveness is set (a proposed list is given below). Isacov and testing...

silabs-robin

Use of $urandom()

7

In core-v-verif there are 8 files that use some variation of `$urandom()`. You are in the "assignees" list of this issue because git believes you authored one or more of...

MikeOpenHWGroup

### Type * Functionally incorrect behavior ### Description When turning on instruction bus tests, the mcause was incorrect. Of course, this should be flagged in the ISS however the BSP...

strichmo

Do-nothing class method overrides

3

In core-v-verif there are 3 files that override a method of a parent class, but only call super.method() with the same arguments. You are in the "assignees" list of this...

MikeOpenHWGroup

VCS Compile error of ISACOV and suggested work-around

9

### Issue Type Compile error under Synopsys VCS (Cadence Xcelium and Metrics Dsim do not have this issue). The offending code in the [ISA coverage model](https://github.com/openhwgroup/core-v-verif/blob/master/lib/uvm_agents/uvma_isacov/cov/uvma_isacov_cov_model.sv#L56) is: ``` cp_rs1: coverpoint...

MikeOpenHWGroup

Diff'ing isacov and tracer logs

7

This issue is motivated by pull request #636. That PR brought in updates to the ISA coverage model and the ability to dump-and-diff tracer vs coverage logs. The coverage model...

MikeOpenHWGroup

define methodology for initializing memory in TB and RM outside of defined program

2

### Type * Methodology The issue is that currently the testbench will initialize memory in the testbench RTL (i.e. the mm_ram) and the reference model in the ISS infrastructure to...

strichmo

### Task Outcome The debug vplan is updated, reviewed and checked in for the E40X. ### Location Information The vplan should be checked into the core-v-verif repository under the cv32e40x....

strichmo

Accessing FP CSRs crashes the debug unit

10

At the request of @MikeOpenHWGroup this is a duplicate of `core-v-mcu` issue [#159](https://github.com/openhwgroup/core-v-mcu/issues/159) ## Accessing FP CSRs crashes the debug unit ### Type Indicate whether the type of problem you...

jeremybennett

OBI_MEMORY_AGENT: conditional Driver and Sequencer instantiation

6

## Type Linter issues: the Driver and Sequencer are unconditionally created in [uvma_obi_memory_agent_c::create_components()](https://github.com/openhwgroup/core-v-verif/blob/1f430b7d805e2459f01c46e6ba58ef1dcbe59419/lib/uvm_agents/uvma_obi_memory/src/comps/uvma_obi_memory_agent.sv#L195) ### Steps to Reproduce Below are a set of links to the specific linter issues: - ['sequencer'...

MikeOpenHWGroup