core-v-verif
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openhwgroup
Functional verification project for the CORE-V family of RISC-V cores.
This issue exists to continue the discussion started with PR #643. The `debug_test_boot_set` test-program has simulator-dependent cycle-timing behaviour. The code in question is in `uvma_debug_drvc::drv_req()`, starting at line [116](https://github.com/openhwgroup/core-v-verif/blob/master/lib/uvm_agents/uvma_debug/uvma_debug_drv.sv#L116). Note...
In [Verification Planning 101](https://github.com/openhwgroup/core-v-verif/blob/master/docs/VerifPlans/VerificationPlanning101.md#passfail-criteria), the Pass/Fail Criteria allows for selection between `Self Checking`, `Signature Check`, `Check against RM`, `Assertion Check`, `Any/All`, `Other` or `N/A`. It has been suggested that the...
Can I ask, for the test above cv32e40p_csr_access_test - does this test also ensure that CSR Registers which should NOT exist, raise an appropriate illegal instruction exception ? so as...
### Task Outcome Using the cv32e40p testbench reimplement step and compare using a scoreboard. The tracer should be replaced by an RVFI interface from the processor. The ### Background information...
### Task Outcome Integrate the ISACOV coverage to the CV32E40P and measure functional coverage ### Background information The ISACOV model is the next-generation functional ISA coverage model for the CV32E40X....
### Task Outcome Implement an OBI Memory UVM Agent. ### Background information The so-called "dut wrappers" for both the [cv32e40p](https://github.com/openhwgroup/core-v-verif/blob/master/cv32e40p/tb/uvmt/uvmt_cv32e40p_dut_wrap.sv) and [cv32e40x](https://github.com/openhwgroup/core-v-verif/blob/master/cv32e40x/tb/uvmt/uvmt_cv32e40x_dut_wrap.sv) instantiate a memory model called [mm_ram](https://github.com/openhwgroup/core-v-verif/blob/master/cv32e40p/tb/core/mm_ram.sv) which supports...
### Task Outcome Strategy for tracking instructions that might be flushed in the pipeline due to interrupts, exceptions, taken branches. ### Background information The processor pipeline may have to perform...
### Task Outcome The cv32e40p compliance tests and regression run with all supported extensions on the new compliance framework from riscv-arch-test ### Background information The current implementation (for v1.0.0 RTL...
### Task Outcome The cv32e40x compliance tests and regression run with all supported extensions on the new compliance framework from riscv-arch-test ### Background information The current implementation is a fork...
## Bug Title: RM and RTL do not match when PC is outside implemented memory ### Type: Functionally incorrect behavior ### Steps to Reproduce make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt Currently...
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Functional verification project for the CORE-V family of RISC-V cores.