core-v-verif
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openhwgroup
Imperas ISS: PUSH and POP type instructions marked as illegal instructions
PUSH and POP type instructions marked as illegal instructions
Type
- Functionally incorrect behavior
Steps to Reproduce
- Use my fork of core-v-verif: [email protected]:silabs-oysteink/core-v-verif.git
- Checkout my branch "silabs-oysteink_zc-decode"
- Check out CV32E40X hash 47d4a57b9e27363ff152c364324bdbbf91a06367
- Modify cv32e40x/rtl/cv32e40x_core.sv to set localparam ZC_EXT= 1
- make clean test TEST=test_zc CV_CORE_PATH=<path_for_cv32e40x_from_above> USE_ISS=1 CV_CORE=cv32e40x
My branch of core-v-verif is modified to enable ZC_EXT for the ISS, and a directed test "zc_test" is added with manually encoded Zc instructions.
The image below shows the test output. After running through some initial Zc instructions, there is a mismatch on the first PUSH instruction. If one comments out the first failing instruction, the next push/pop type instruction will also mismatch on mcause.
@silabs-hfegran, this issue looks like it has gone stale. What is its status?
@silabs-hfegran, this issue looks like it has gone stale. What is its status?
@MikeOpenHWGroup, I am uncertain about the current status of this issue - perhaps @silabs-mateilga or @silabs-oysteink can give an update here next week?
I am still assigned on this issue - is there something for me to look at ? I think this is probably pending fixes to the RVFI interface to drive multiple destination registers in a single retirement ?
@eroom1966 I think this issue is deprecated now, I'll get Øystein to close it, and we'll open new issues if there is still something here. That said, the RVFI interface is expanded to drive multiple registers, and has been for weeks now. The signals are the set of rvfi_gpr_* found here.
This issue is likely out-of-date. I'll close it, and if the issue comes back we can make a new or reopen this one.