core-v-verif
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openhwgroup
Functional verification project for the CORE-V family of RISC-V cores.
Hello, While working on the verification of HPDcache, I observed that ready signals of AXI2MEM are internally driven to 1. The readme of AXI2MEM says that user should drive these...
This task is related to #2393. We have determined that VCS versions U-2023.03-SP1 and V-2023.12-1 resolve the issue and functional coverage code constructs such as `bins rd[] = {[0:31]} with...
In pull-request #2394 I made a comment about using `illegal_bins`. An illegal bin is excluded from coverage, but if the goal is to exclude bins it is best to use...
Issue observed and reproducible on recent versions of `core-v-verif` code including the latest master (commit 4e6e8604f): when attemptring a CVA6 Spike tandem run with VCS-UVM (envariable `DV_SIMULATORS` contains `vcs-uvm` and...
Hi y'all, I'm trying to verify CV32E40P core. I can't use/purchase Imperas solutions due to economic issues. So, I have to use freeware options. Is there any configuration/settings/files about to...
**Functionally incorrect behavior:** the core cntrl cfg agent does not mark CSRs `mtinst` and `mtval2` as unsupported in the absence of the `H` (hypervisor) extension. As a result, Spike tandem...
Bring Yaml support up to date with Spike evolutions. Fix race conditions and correctness issues in yaml-cpp build.
This is a bug for cv32a65x configuration !! According to the [CV32A65X Spec](https://docs.openhwgroup.org/projects/cva6-user-manual/04_cv32a65x/riscv/priv.html#_machine_status_mstatus_and_mstatush_registers), the mtvec only support direct mode, so the mtvec[1:0] should be always equal to zero, this is...
This PR adds the changes to Spike necessary to support the reference model in #2432. I have attempted to split it into two main contributions: - Added spike support for...
[cv_dv_utils generic_agent] by default it is an active agent now [cv_dv_utils tp_trans] added a python script to create OHG verification TestPlan [cv_dv_utils bp] added force and release task
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Functional verification project for the CORE-V family of RISC-V cores.