uvm topic

Customized UVM Report Server

kaushalmodi

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Nic30

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cocotb

Code generation tool for control and status registers

rggen

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

tymonx

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

chipsalliance

AMBA AXI VIP

taichi-ishitani

Awesome ASIC design verification

troyguo

Functional verification project for the CORE-V family of RISC-V cores.

openhwgroup

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Juniper